The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that are linked by metal wiring. Metal interconnects are typically constructed by patterning trenches and vias in a photosensitive layer and then etching the pattern into one or more dielectric layers. A damascene process is generally employed to fill the etched openings and planarize the deposited metal. As the dimension of the wiring and the intermetal dielectric layer distances have steadily decreased in order to satisfy a constant demand for higher performance in electronic devices, the challenge to prevent crosstalk between the wiring has been a key focus for semiconductor manufacturers. One important improvement in preventing capacitance coupling between metal layers has been the introduction of low k dielectric materials. A commonly used SiO2 dielectric layer having a dielectric constant (k) of about 4 is being replaced by other materials with a k value of between 2 and 3.
Dielectric layers are often deposited by a chemical vapor deposition (CVD) method or by a plasma enhanced CVD (PECVD) process. Low k dielectric materials that are deposited in this manner include carbon doped SiO2, fluorine doped SiO2, fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), and “Black Diamond” from Applied Materials. Other low k materials such as polyimides, silsesquioxanes, polyarylethers, and SiLK from Novellus are available in solution and can be coated on a substrate by a spin-on technique. With a spin-on layer, the coated film is normally cured by baking the substrate in an oven. This method is costly in terms of a low throughput since a considerable amount of time is required to carefully ramp up the furnace to an elevated temperature once the substrates are loaded in the chamber. Furthermore, this curing method is expensive because a great deal of energy is expended to maintain a large enclosed area at a high temperature. The batch process in which a boat of substrates is treated in a furnace is no longer compatible with a single wafer mode necessary for high throughput when handling 300 mm size substrates.
Another increasingly important concern associated with shrinking device dimensions is the cleanliness of the fabrication process. Air handling systems are becoming more complex in order to remove particles from the air that can cause a defect in a device. Trace amounts of metals and organic solvents must be removed from a substrate by cleaning steps to prevent contamination that leads to a loss in device performance. Residues from etching steps and from photoresist removal methods are also a cause for concern. To avoid a costly rework process that involves repeating several steps in a sequence, a cleaning step is usually inserted at points in manufacturing scheme where a defect free surface is mandatory before the next process is started.
A process is described in U.S. Pat. No. 6,156,661 for removing trace amounts of amines following an amine based treatment such as a photoresist strip. The treatment involves an aqueous solution containing an organic acid that is maintained within a pH range of about 4 to 6 by a buffering agent like hydroxylamine. The solution can also contain an oxidizer to repair metal surfaces that are damaged by an etch or by a polishing step. Additionally, the method can reduce the level of mobile ions and unwanted transition metal ions that are absorbed on a substrate.
Another method for treating a substrate in preparation for a subsequent process step is mentioned in U.S. Pat. No. 6,319,819. This method relates to removing oxides from copper surfaces to prevent electromigration, improve adhesion, and decrease contact resistance. A metal such as Mg, Cr, Ti, Ta, or Ni is deposited by a physical vapor technique and diffuses into the upper regions of a copper layer where it reduces copper oxide. After a polishing step, a passivation layer remains on the copper to prevent further oxide formation.
Yet another method of removing organic materials from a substrate is by subjecting the substrate to a supercritical fluid (SCF) such as CO2 or ethylene. U.S. Pat. No. 6,346,484 provides details for removing a sacrificial place holder (SPH) material such as a polysilsesquioxane through a porous bridge layer. The extraction occurs at a high pressure of about 100 atmospheres and at an elevated temperature. The solute and SCF are transported to a separator which is at a lower temperature to precipitate the solute. Then the SCF is repressurized and recycled back to the extraction chamber. The bridge layer is then sealed to form an air gap with a dielectric constant of 1 between metal interconnects.
In U.S. Pat. No. 6,306,754, a SCF is used to remove a temporary structural solid through a dielectric layer such as porous SiO2. Residual alcohol solvent within the SiO2 is also removed to effect a cure process. An average pore size of from 2 to 50 nm is specified and pores preferably represent between 5 and 30% of the total volume of the SiO2 layer that is spin coated from a solution of tetraethylorthosilicate (TEOS) in ethanol and water. The SCF process may include a co-solvent such as a ketone or alcohol and takes place in a chamber heated between 30° C. and 100° C. The upper temperature is limited since the temporary structural solid is a photoresist that is sensitive to temperatures above 100° C. where it could decompose and be more difficult to extract.
Although the prior art teaches the application of SCF to remove solvent from a dielectric layer, the method is restricted to SiO2 with a maximum pore volume of 30% and operating conditions below 100° C. There is a need to expand the range of applicability to other low k spin-on materials such as organic dielectric layers that have pore sizes as small as 1 nm, pore volumes above 30%, and where extraction temperatures of up to 150° C. are preferred. Furthermore, it is desirable to employ a co-solvent that can lower the dielectric constant and strengthen the hardness and elastic modulus of the treated layer as it is being cured.